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Ultralow Noise VGAs with Preamplifier and Programmable RIN AD8331/AD8332
FEATURES
Ultralow noise preamplifier Voltage noise = 0.74 nV/Hz Current noise = 2.5 pA/Hz 3 dB bandwidth: 120 MHz Low power: 125 mW/channel Wide gain range with programmable postamp -4.5 dB to +43.5 dB +7.5 dB to +55.5 dB Low output-referred noise: 48 nV/Hz typical Active input impedance matching Optimized for 10-/12-bit ADCs Selectable output clamping level Single 5 V supply operation Available in space-saving chip scale package
VPS1 26 VMID COM1 23 +19dB + INH1 27 LMD1 28 [(-48 to 0) + 21] dB - LNA 1 - + VGA 1 POST AMP1 3.5dB/15.5dB
17 VOH1
FUNCTIONAL BLOCK DIAGRAM
LON1 LOP1
25 24
VIP1
22
VIN1
21
VPSV
15
VCM1
20
VCM2
9
HILO
19
16 VOL1
BIAS (VMID)
BIAS AND INTERPOLATOR
GAIN INT
10 GAIN
LMD2 1 INH2 2
- LNA 2 +
VPS2 3 CLAMP
03199-B-001
COM2 6
4 5 7 8 14 18 11
LON2
LOP2
VIP2
VIN2
APPLICATIONS
50
Figure 1. AD8332 Shown 28-Lead TSSOP
VGAIN = 1V 40 0.8V 30 0.6V 20 0.4V 10 0.2V 0 -10 -20 100k 0V
Ultrasound and sonar time-gain control High performance AGC systems I/Q signal processing High speed dual ADC driver
GENERAL DESCRIPTION
The AD8331/AD8332 are single- and dual-channel ultralow noise, linear-in-dB, variable gain amplifiers. Although optimized for ultrasound systems, they are usable as low noise variable gain elements at frequencies up to 120 MHz. Each channel consists of an ultralow noise preamplifier (LNA), an X-AMP(R) VGA with 48 dB of gain range, and a selectable gain postamplifier with adjustable output limiting. The LNA gain is 19 dB with a single-ended input and differential outputs capable of accurate, programmable active input impedance matching by selecting an external feedback resistor. Active impedance control optimizes noise performance for applications that benefit from input matching. The 48 dB gain range of the VGA makes these devices suitable for a variety of applications. Excellent bandwidth uniformity is maintained across the entire range. The gain control interface provides precise linear-in-dB scaling of 50 dB/V for control voltages between 40 mV and 1 V. Factory trim ensures excellent part-to-part and channel-to-channel gain matching. Differential signal paths lead to superb second and third order distortion performance and low crosstalk.
GAIN (dB)
1M
10M FREQUENCY (Hz)
100M
1G
Figure 2. Frequency Response vs. Gain
The VGA's low output-referred noise is advantageous in driving high speed differential ADCs. The gain of the postamplifier may be pin selected to 3.5 dB or 15.5 dB to optimize gain range and output noise for 12-bit or 10-bit converter applications. The output may be limited to a user-selected clamping level, preventing input overload to a subsequent ADC. An external resistor adjusts the clamping level. The operating temperature range is -40C to +85. The AD8331 is available in a 20-lead QSOP package, and the AD8332 in 28-lead TSSOP and 32-lead LFCSP packages. They require a single 5 V supply, and the quiescent power consumption is 125 mW/ch. A power-down (enable) pin is provided.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2003 Analog Devices, Inc. All rights reserved.
03199-C-002
+ VGA 2 - POST AMP2 COMM ENB RCLMP
13 VOL2
12 VOH2
AD8331/AD8332 TABLE OF CONTENTS
REVISION HISTORY.................................................................. 2 Overload ...................................................................................... 24 AD8331, AD8332--Specifications.................................................. 3 Optional Input Overload Protection. ...................................... 25 Absolute Maximum Ratings............................................................ 6 Layout, Grounding, And Bypassing ......................................... 25 ESD CAUTION ............................................................................ 6 Multiple Input Matching ........................................................... 25 AD8331, AD8332--Typical Performance Characteristics .......... 7 Disabling the LNA...................................................................... 25 Test Circuits..................................................................................... 15 Measurement Considerations................................................... 26 Theory of Operation ...................................................................... 17 Ultrasound TGC Application ................................................... 26 Overview...................................................................................... 17 Pin Configuration and Function Descriptions........................... 30 Low Noise Amplifier (LNA)...................................................... 17 AD8331........................................................................................ 30 Variable Gain Amplifier............................................................. 19 AD8332........................................................................................ 31 Postamplifier ............................................................................... 21 Outline Dimensions ....................................................................... 32 Applications..................................................................................... 22 Ordering Guide .......................................................................... 32 LNA - External Components ................................................... 22 Driving ADCs ............................................................................. 24
REVISION HISTORY
Revision C 11/03--Data Sheet Changed from REV. B to REV. C Addition of New Part...........................................................Universal Changes to Figures ...............................................................Universal Updated Outline Dimensions..........................................................32 5/03--Data Sheet Changed from REV. A to REV. B Edits to Ordering Guide....................................................................32 Edits to Ultrasound TGC Application section................................25 Added Figure 71, Figure 72, and Figure 73......................................26 Updated Outline Dimensions............................................................31 2/03--Data Sheet Changed from REV. 0 to REV. A Edits to Ordering Guide.....................................................................32
Rev. C | Page 2 of 32
AD8331/AD8332 AD8331, AD8332--SPECIFICATIONS
Table 1. TA = 25C, VS = 5 V, RL = 500 , RS = RIN = 50 , RFB = 280 , CSH = 22 pF, f = 10 MHz, RCLMP = , CL = 1 pF, VCM pin floating, -4.5 dB to +43.5 dB gain (HILO = LO), and differential output voltage, unless otherwise specified.
Parameter LNA CHARACTERISTICS Gain Conditions Single-Ended Input to Differential Output Input to Output (Single-Ended) AC-Coupled RFB = 280 RFB = 412 RFB = 562 RFB = 1.13 k RFB = Single-Ended, Either Output VOUT = 0.2 V p-p RS = 0 , HI or LO Gain, RFB = , f = 5 MHz RFB = , HI or LO Gain, f = 5 MHz f = 10 MHz, LOP Output RS = RIN = 50 RS = 50 , RFB = VOUT = 0.5 V p-p, Single-Ended, f = 10 MHz Pins LON, LOP VOUT = 0.2 V p-p VOUT = 2 V p-p LO Gain HI Gain RS = 0 , HI or LO Gain, RFB = , f = 5 MHz VGAIN = 1.0 V RS = RIN = 50 , f = 10 MHz, Measured RS = RIN = 200 , f = 5 MHz, Simulated RS = 50 , RFB = , f = 10 MHz, Measured RS = 200 , RFB = , f = 5 MHz, Simulated VGAIN = 0.5 V, LO Gain VGAIN = 0.5 V, HI Gain DC to 1 MHz RL 500 , Unclamped, Either Pin Min Typ 19 13 275 50 75 100 200 6 13 5 130 650 0.74 2.5 3.7 2.5 -56 -70 165 120 110 300 1200 0.82 Max Unit dB dB mV k pF MHz V/s nV/Hz pA/Hz dB dB dBc dBc mA MHz MHz V/s V/s nV/Hz
Input Voltage Range Input Resistance
Input Capacitance Output Impedance -3 dB Small Signal Bandwidth Slew Rate Input Voltage Noise Input Current Noise Noise Figure Active Termination Match Unterminated Harmonic Distortion @ LOP1 or LOP2 HD2 HD3 Output Short-Circuit Current LNA + VGA CHARACTERISTICS -3 dB Small Signal Bandwidth -3 dB Large Signal Bandwidth Slew Rate Input Voltage Noise Noise Figure Active Termination Match
4.15 2.0 2.5 1.0 48 178 1 VCM 1.125 4.5
dB dB dB dB nV/Hz nV/Hz V V p-p +50 +100 mV mV mA
Unterminated
Output-Referred Noise Output Impedance, Postamplifier Output Signal Range, Postamplifier Differential Output Offset Voltage Differential Common-Mode Output Short-Circuit Current
VGAIN = 0.5 V
-50 -125
5 -25 45
Rev. C | Page 3 of 32
AD8331/AD8332
Parameter Harmonic Distortion HD2 HD3 HD2 HD3 Input 1 dB Compression Point Two-Tone Intermodulation Distortion (IMD3) Output Third Order Intercept Channel-to-Channel Crosstalk (AD8332) Overload Recovery Conditions VGAIN = 0.5 V, VOUT = 1 V p-p f = 1 MHz f = 10 MHz VGAIN = 0.25 V, VOUT = 1 V p-p, f = 1 MHz-10 MHz VGAIN = 0.72 V, VOUT = 1 V p-p, f = 1 MHz VGAIN = 0.5 V, VOUT = 1 V p-p, f = 10 MHz VGAIN = 0.5 V, VOUT = 1 V p-p, f = 1 MHz VGAIN = 0.5 V, VOUT = 1 V p-p, f = 10 MHz VGAIN = 0.5 V, VOUT = 1 V p-p, f = 1 MHz VGAIN = 1.0 V, VIN = 50 mV p-p/1 V p-p, f = 10 MHz 5 MHz < f < 50 MHz, Full Gain Range 0.05 V < VGAIN < 0.10 V 0.10 V < VGAIN < 0.95 V 0.95 V < VGAIN < 1.0 V 0.1 V < VGAIN < 0.95 V 0.1 V < VGAIN < 0.95 V -1 -1 -2 Min Typ -88 -85 -68 -65 7 -80 -72 38 33 -84 5 2 +0.5 0.3 -1 0.2 0.1 +2 +1 +1 Max Unit dBc dBc dBc dBc dBm1 dBc dBc dBm dBm dB ns ns dB dB dB dB dB
Group Delay Variation ACCURACY Absolute Gain Error2
Gain Law Conformance3 Channel-to-Channel Gain Matching GAIN CONTROL INTERFACE (Pin GAIN) Gain Scaling Factor Gain Range Input Voltage (VGAIN) Range Input Impedance Response Time COMMON-MODE INTERFACE (Pin VCMn) Input Resistance Output CM Offset Voltage Voltage Range ENABLE INTERFACE (Pins ENB, ENBL, ENBV) Logic Level to Enable Power Logic Level to Disable Power Input Resistance
0.10 V < VGAIN < 0.95 V LO Gain HI Gain
48 dB Gain Change to 90% Full Scale
50 -4.5 to +43.5 +7.5 to +55.5 0 to 1.0 10 750
dB/V dB dB V M ns
Current Limited to 1 mA VCM = 2.5 V VOUT = 2.0 V p-p
-125
30 -25 1.5 to 3.5
+100
mV V
2.25 0 Pin ENB Pin ENBL Pin ENBV VINH = 30 mV p-p VINH = 150 mV p-p 25 40 70 300 4
5 1.0
Power-Up Response Time HILO GAIN RANGE INTERFACE (Pin HILO) Logic Level to Select HI Gain Range Logic Level to Select LO Gain Range Input Resistance
V V k k k s ms
2.25 0 50
5 1.0
V V k
1 2 3
All dBm values are referred to 50 , unless otherwise noted. Conformance to theoretical gain expression (see Equation 1). Conformance to best fit dB linear curve. Rev. C | Page 4 of 32
AD8331/AD8332
Parameter OUTPUT CLAMP INTERFACE (Pin RCLMP; HI or LO Gain) Accuracy HILO = LO HILO = HI MODE INTERFACE (Pin MODE) Logic Level for Positive Gain Slope Logic Level for Negative Gain Slope Input Resistance POWER SUPPLY (Pins VPS1, VPS2, VPSV, VPSL, VPOS) Supply Voltage Quiescent Current per Channel Power Dissipation per channel Disable Current AD8332 (VGA and LNA) AD8331 (VGA and LNA) AD8332 (ENBL) AD8332 (ENBV) AD8331 (ENBL) AD8331 (ENBV) PSRR Conditions Min Typ Max Unit
RCLMP = 2.74 k, VOUT = 1 V p-p (Clamped) RCLMP = 2.21 k, VOUT = 1 V p-p (Clamped)
50 75
mV mV
0 2.25 200
1.0 5
V V k
4.5 No Signal
5.0 25 125 300 240 12 13 11 14 -68
5.5
V mA mW A A mA mA mA mA dB
600 400
Each Channel Each Channel
VGAIN = 0, f = 100 kHz
Rev. C | Page 5 of 32
AD8331/AD8332 ABSOLUTE MAXIMUM RATINGS
Table 2. Absolute Maximum Ratings
Parameter Voltage Supply Voltage (VPSn, VPSV, VPSL, VPOS) Input Voltage (INHn) ENB, ENBL, ENBV, HILO Voltage GAIN Voltage Power Dissipation RU-28 Package (AD8332)4 CP-32 Package (AD8332)5 RQ-20 Package (AD8331)4 Temperature Operating Temperature Storage Temperature Lead Temperature (Soldering 60 sec) JA RU-28 Package (AD8332)4 CP-32 Package (AD8332)5 RQ-20 Package (AD8331)4 JC RU-28 Package (AD8332)4 CP-32 Package (AD8332)5 RQ-20 Package (AD8331)4 Rating 5.5 V VS + 200 mV VS + 200 mV 2.5 V 0.96 W 1.97 W 0.78 W -40C to +85C -65C to +150C 300C 68C/W 33C/W 83C/W 14C/W 33C/W n/a
Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
4 5
Four-Layer JEDEC Board (2S2P). Exposed pad soldered to board, nine thermal vias in pad -- JEDEC 4-Layer Board J-STD-51-9.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. C | Page 6 of 32
AD8331/AD8332 AD8331, AD8332--TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25C, VS = 5 V, RL = 500 , RS = RIN = 50 , RFB = 280 , CSH = 22 pF, f = 10 MHz, RCLMP = , CL = 1 pF, VCM = 2.5 V, -4.5 dB to +43.5 dB gain (HILO = LO), and differential signal voltage, unless otherwise specified.
60 50 HILO = HI 40
% OF UNITS
GAIN (dB)
40 50 SAMPLE SIZE = 80 UNITS VGAIN = 0.5V
30 MODE = LO 20 10 HILO = LO 0
30
MODE = HI (AC PACKAGE ONLY)
20
10
03199-C-003
-10 0 0.2 0.4 0.6 VGAIN (V) 0.8 1.0 1.1
0 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 GAIN ERROR (dB)
0.5
Figure 3. Gain vs. VGAIN and MODE (MODE Available on AC Package)
2.0 1.5 1.0
Figure 6. Gain Error Histogram
25 SAMPLE SIZE = 50 UNITS 20 VGAIN = 0.2V 15
GAIN ERROR (dB)
-40C 0.5
+25C % OF UNITS
10 5 0 25 20 15
03199-C-004
03199-C-007
0 -0.5 -1.0 -1.5 -2.0 0 0 .2 0.4 0.6 VGAIN (V) 0.8 1.0 +85C
VGAIN = 0.7V
10 5
-0.11 -0.09 -0.01 0.01 0.09 0.11 0.03 0.05 0.07 0.13 0.15 0.17 -0.17 -0.15 -0.13 -0.07 -0.05 -0.03 0.19 0.21
1G
1.1
0
Figure 4. Absolute Gain Error vs. VGAIN at Three Temperatures
2.0 1.5 1.0
GAIN ERROR (dB)
CHANNEL-TO-CHANNEL GAIN MATCH (dB)
Figure 7. Gain Match Histogram for VGAIN = 0.2 V and 0.7 V
50 VGAIN = 1V 40 0.8V
10MHz
0.5 1MHz 0 -0.5 30MHz -1.0
30 0.6V
GAIN (dB)
20 0.4V 10 0.2V 0
70MHz
-1.5 -2.0 0 0.2 0.4 0.6 VGAIN (V) 0.8 1.0
03199-C-005
1.1
-20 100k
1M
10M FREQUENCY (Hz)
100M
Figure 5. Absolute Gain Error vs. VGAIN at Various Frequencies Figure 8. Frequency Response for Various Values of VGAIN
Rev. C | Page 7 of 32
03199-C-008
-10
0V
03199-C-006
AD8331/AD8332
60 VGAIN = 1V 50 40
0 VOUT = 1 V p-p -10
0.8V
-20
30
CROSSTALK (dB)
0.6V
-30 -40 -50 VGAIN = 1V -60 -70 0.9V 0.7V -80 -90 100k 0.5V 1M 10M FREQUENCY (Hz)
03199-C-012
GAIN (dB)
0.4V 0.2V 0V
03199-C-009
20 10
0 -10 100k
0.4V
1M
10M FREQUENCY (Hz)
100M
1G
100M
Figure 9. Frequency Response for Various Values of VGAIN, HILO = HI
30 VGAIN = 0.5 V 20 10
GAIN (dB)
50
Figure 12. Channel-to-Channel Crosstalk vs. Frequency for Various Values of VGAIN
0.1F COUPLING
RIN = R S = 50, 75, 100 RIN = R S = 1k
GROUP DELAY (ns)
45 40 35 30 25 20 15 10 5 0 100k
RIN = R S = 500 0 RIN = R S = 200 -10 -20 -30 -40 100k
1F COUPLING
03199-C-010
1M
10M FREQUENCY (Hz)
100M
1G
1M
10M FREQUENCY (Hz)
100M
Figure 10. Frequency Response for Various Matched Source Impedances
30 VGAIN = 0.5V RFB = 20 10
20
Figure 13. Group Delay vs. Frequency
HI GAIN 10 0 T = +25C T = -40C T = +25C T = +85C
OFFSET VOLTAGE (mV)
-10 -20 20 LO GAIN 10 0 T = -40C T = +85C T = -40C T = +85C
GAIN (dB)
0 -10 -20 -30 -40 100k
03199-C-011
-10 T = -40C -20 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
1M
10M FREQUENCY (Hz)
100M
1G
1.1
VGAIN (V)
Figure 11. Frequency Response, Unterminated, RS = 50
Figure 14. Representative Differential Output Offset Voltage vs. VGAIN at Three Temperatures
Rev. C | Page 8 of 32
03199-C-014
T = +25C
03199-C-013
AD8331/AD8332
35 SAMPLE SIZE = 100 0.2V < VGAIN < 0.7V
25j RIN = 50 , RFB = 270 50j 100j f = 100kHz
30
25
% TOTAL
RIN = 75, RFB = 412
20
RIN = 100, RFB = 549
15
0 17
10
03199-B-015
5
RIN = 200, RFB = 1.1k
0
49.6
49.7
49.8
49.9
50.0
50.1
50.2
50.3
50.4
50.5
-25j
GAIN SCALING FACTOR
RIN = 6k, RFB =
03199-B-018
Figure 15. Gain Scaling Factor Histogram
-50j
-100j
100 SINGLE ENDED, PIN VOH OR VOL RL =
Figure 18. Smith Chart, S11 vs. Frequency, 0.1 MHz to 200 MHz for Various Values of RFB
20
RIN = 50, 75, AND 100 RIN = 200
OUTPUT IMPEDANCE ()
15
10
10 5
GAIN (dB)
RIN = 1k RIN = 500
RIN = 200
1
0 -5
03199-C-016
-10 -15 -20 100k
03199-C-019
0.1 100k
1M
10M FREQUENCY (Hz)
100M
Figure 16. Output Impedance vs. Frequency
1M
10M FREQUENCY (Hz)
100M
1G
10k
Figure 19. LNA Frequency Response, Single-Ended, for Various Values of RIN
RFB = , CSH = 0pF
20 15
INPUT IMPEDANCE ()
RFB = 6.65k, CSH = 0pF 1k RFB = 3.01k, CSH = 0pF
10 RFB = 5
RFB = 1.1k, CSH = 1.2pF 100 RFB = 549, CSH = 8.2pF
GAIN (dB)
03199-C-017
0 -5
RFB = 412, CSH = 12pF RFB = 270, CSH = 22pF 10 100k
-10 -15 -20 100k
03199-C-020
1M FREQUENCY (Hz)
10M
100M
1M
10M FREQUENCY (Hz)
100M
1G
Figure 17. LNA Input Impedance vs. Frequency for Various Values of RFB and CSH
Figure 20. LNA Frequency Response, Unterminated, Single-Ended
Rev. C | Page 9 of 32
AD8331/AD8332
500 f = 10MHz
OUTPUT-REFERRED NOISE (nV/ Hz)
1.00 0.95 0.90 RS = 0, RFB = , VGAIN = 1V, f = 10MHz
400
INPUT NOISE (nV/ Hz)
0.85 0.80 0.75 0.70 0.65 0.60
300
200
HILO = HI
100 HILO = LO 0
03199-C-021
0.55 0.50 -50 -30 -10 10 30 50 70
0
0.2
0.4 VGAIN (V)
0.6
0.8
1.0
90
TEMPERATURE (C)
Figure 21. Output-Referred Noise vs. VGAIN
1.6 1.4 RS = 0, RFB = , VGAIN = 1V HILO = LO OR HI
Figure 24. Short-Circuit Input-Referred Noise vs. Temperature
10 f = 5MHz, RFB = , VGAIN = 1V
INPUT NOISE (nV/ Hz)
1.0 0.8 0.6 0.4 0.2 0 100k
03199-C-022
INPUT NOISE (nV/ Hz)
1.2
1.0
0.1 1 10 100 SOURCE RESISTANCE () 1k
1M
10M FREQUENCY (Hz)
100M
Figure 22. Short-Circuit Input-Referred Noise vs. Frequency
100 RS = 0, RFB = , HILO = LO OR HI, f = 10MHz
Figure 25. Input-Referred Noise vs. RS
7 INCLUDES NOISE OF VGA 6 5 RIN = 50 4 75 3 2 RFB =
03199-C-023
INPUT NOISE (nV/ Hz)
10
NOISE FIGURE (dB)
100 200
1
SIMULATION 0 50 100 SOURCE RESISTANCE () 1k
0.1 0
0.2
0.4
0.6 VGAIN (V)
0.8
1.0
Figure 23. Short-Circuit Input-Referred Noise vs. VGAIN
Figure 26. Noise Figure vs. RS for Various Values of RIN
Rev. C | Page 10 of 32
03199-C-026
1
03199-C-025
RS = THERMAL NOISE ALONE
03199-C-024
AD8331/AD8332
50 f = 10MHz, RS = 50 45
-30 f = 10MHz VOUT = 1V p-p -40
HARMONIC DISTORTION (dBc)
40 HILO = LO, RIN = 50
NOISE FIGURE (dB)
35 HILO = HI, RIN = 50 30 25 20 15 10 5 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 VGAIN (V) 0.8 0.9 1.0 HILO = HI, RFB =
03199-C-027
-50 -60 -70 -80 -90
HILO = LO, HD3 HILO = LO, HD2
HILO = LO, RFB =
HILO = HI, HD2 HILO = HI, HD3
03199-C-030
1.1
-100 0 200 400 600 800 1.0k 1.2k RLOAD () 1.4k 1.6k 1.8k
2.0k
Figure 27. Noise Figure vs. VGAIN
30 HILO = HI, RIN = 50 HILO = HI, RFB =
Figure 30. Harmonic Distortion vs. RLOAD
-40 f = 10MHz VOUT = 1V p-p -50
25
HARMONIC DISTORTION (dBc)
NOISE FIGURE (dB)
20 HILO = LO, RIN = 50 15
-60
HILO = LO, HD3
HILO = HI, HD2
-70 HILO = HI, HD3
10 HILO = LO, RFB =
03199-C-028
-80
HILO = LO, HD2
03199-C-031
5
-90
0 10
f = 10MHz, RS = 50 15 20 25 35 30 40 GAIN (dB) 45 50 55
60
-100 0
10
20 30 CLOAD (pF)
40
50
Figure 28. Noise Figure vs. Gain
0 -10 G = 30dB VOUT = 1VP-P
Figure 31. Harmonic Distortion vs. CLOAD
-40 f = 10MHz GAIN = 30 dB -50 HILO = HI, HD3 HILO = LO, HD3 -60 HILO = LO, HD2
HARMONIC DISTORTION (dBc)
-30 -40 -50 -60 -70 -80 HILO = LO, HD2 HILO = HI, HD2
HILO = LO, HD3
HARMONIC DISTORTION (dBc)
-20
-70
HILO = HI, HD2
HILO = HI, HD3
03199-C-029
-80
-90 -100 1M 10M FREQUENCY (Hz)
100M
-100 0 1 2 VOUT (V p-p) 3 4
Figure 29. Harmonic Distortion vs. Frequency
Figure 32. Harmonic Distortion vs. Differential Output Voltage
Rev. C | Page 11 of 32
03199-C-032
-90
AD8331/AD8332
0 VOUT = 1V p-p -20 INPUT RANGE LIMITED WHEN HILO = LO HILO = LO, HD2 HILO = HI, HD2
-20 0 -10 VOUT = 1V p-p COMPOSITE (f1 + f2) G = 30dB
DISTORTION (dBc)
-40
IMD3 (dBc)
03199-C-033
HILO = LO, HD3
-30 -40 -50 -60
-60
-80 HILO = HI, HD3
-70 -80 -90 1M
03199-C-036
-100
-120
0
0.1
0.2
0.3
0.4
0.5 VGAIN (V)
0.6
0.7
0.8
0.9
1.0
10M FREQUENCY (Hz)
100M
Figure 33. Harmonic Distortion vs. VGAIN, f = 1 MHz
0 VOUT = 1V p-p -20
INPUT RANGE LIMITED WHEN HILO = LO
Figure 36. IMD3 vs. Frequency
40 35 HILO = HI, 1MHz HILO = LO, 10MHz HILO = HI, 10MHz HILO = LO, 1MHz
DISTORTION (dBc)
-40
OUTPUT IP3 (dBm)
HILO = LO, HD2 HILO = LO, HD3
30 25 20 15
-60
-80 HILO = HI, HD2
03199-C-034
VOUT = 1V p-p COMPOSITE (f1 + f2) 10 5 0 0
03199-C-037
-100
HILO = HI, HD3
-120 0 0.1 0.2 0.3 0.4 0.5 VGAIN (V) 0.6 0.7 0.8 0.9 1.0
0.1
0.2
0.3
0.4
0.5 VGAIN (V)
0.6
0.7
0.8
0.9
1.0
Figure 34. Harmonic Distortion vs. VGAIN, f = 10 MHz
10
Figure 37. Output Third Order Intercept vs. VGAIN
2mV 5 f = 10MHz 0
100 90
INPUT POWER (dBm)
HILO = HI -5 -10 -15
HILO = LO
10
-20 -25 -30 0 0.1 0.2 0.3 0.4 0.5 0.6 VGAIN (V) 0.7 0.8 0.9
03199-C-035
0 03199-C-038
50mV
10ns
1.0
Figure 38. Small Signal Pulse Response, G = 30 dB, Top: Input, Bottom: Output Voltage, HILO = HI or LO
Figure 35. Input 1 dB Compression vs. VGAIN
Rev. C | Page 12 of 32
AD8331/AD8332
5 20mV
100 90
4 HILO = HI
VOUT (V p-p)
3
HILO = LO
2
10 0 03199-C-039
1
03199-C-042
500mV
10ns
0
Figure 39. Large Signal Pulse Response, G = 30 dB, HILO = HI or LO, Top: Input, Bottom: Output Voltage
0
10
20
30 RCLMP (k)
40
50
Figure 42. Clamp Level vs. RCLMP
2 G = 30dB CL = 50pF
4 G = 40dB 3
1
INPUT CL = 0pF
RCLMP = 48.1k 2 1
RCLMP = 16.5k
VOUT (V)
0
VOUT (V)
0 -1
RCLMP = 7.15k
RCLMP = 2.67k
-1
03199-C-040
-2 -3 -4 -10
03199-C-043
INPUT IS NOT TO SCALE -2 -40 -30 -20 -10 0 10
20
30
40
50
60
70
80
TIME (ns)
0
10
Figure 40. Large Signal Pulse Response for Various Capacitive Loads, CL = 0 pF, 10 pF, 20 pF, 50 pF
20 30 TIME (ns)
40
50
60
Figure 43. Clamp Level Pulse Response
500mV
100 90
200mV
10 0
03199-B-041
200mV
400ns
100ns
Figure 41. Pin GAIN Transient Response, Top: VGAIN, Bottom: Output Voltage
Figure 44. LNA Overdrive Recovery, VINH 0.05 V p-p to 1 V p-p Burst, VGAIN = 0.27 V, VGA Output Shown
Rev. C | Page 13 of 32
03199-B-044
AD8331/AD8332
50mV
100 90
2V
10 0
03199-B-045 03199-B-048
100ns
1V
1ms
Figure 45. VGA Overdrive Recovery, VINH 4 mV p-p to 70 mV p-p Burst, VGAIN = 1 V, VGA Output Shown Attenuated 24 dB
0 -10
50mV
Figure 48. Enable Response, Large Signal, Top: VENB, Bottom: VOUT, VINH = 150 mV p-p
VPS1, VGAIN = 0.5V -20 VPSV, VGAIN = 0.5V
100 90
PSRR (dB)
-30 -40 -50 VPS1, VGAIN = 0V -60
10 0
03199-B-046
-70
100ns
-80 100k
1M
10M FREQUENCY (Hz)
100M
Figure 46. VGA Overdrive Recovery, VINH 4 mV p-p to 275 mV p-p Burst, VGAIN = 1 V, VGA Output Shown Attenuated 24 dB
60
2V
Figure 49. PSRR vs. Frequency (No Bypass Capacitor)
QUIESCENT SUPPLY CURRENT (mA)
55 50
VGAIN = 0.5V
AD8332 45 40 35 30 25 20 -40
AD8331
03199-C-050
200mV
1ms
03199-B-047
-20
0
Figure 47. Enable Response, Top: VENB, Bottom: VOUT, VINH = 30 mV p-p
20 40 TEMPERATURE (C)
60
80
100
Figure 50. Quiescent Supply Current vs. Temperature
Rev. C | Page 14 of 32
03199-C-049
AD8331/AD8332 TEST CIRCUITS
NETWORK ANALYZER
50 OUT
50 IN
1.8nF 270 FB* 120nH 22pF 0.1F 237 28 DUT 237 28 *FERRITE BEAD
03199-C-051
0.1F INH LMD
0.1F
1:1
0.1F
Figure 51. Gain and Bandwidth Measurements
OSCILLOSCOPE 1.8nF 270 FB* 120nH 22pF 50 0.1F 0.1F *FERRITE BEAD 237 0.1F INH LMD 0.1F 28 DUT 237 28
03199-C-052
50 IN 1:1
Figure 52. Transient Measurements
A
G
B
SPECTRUM ANALYZER
49
FB* 0.1F 120nH 1 22pF
0.1F INH LMD DUT 0.1F 1:1
50 IN
50
0.1F
*FERRITE BEAD
03199-C-053
Figure 53. Used for Noise Measurements
Rev. C | Page 15 of 32
AD8331/AD8332
SPECTRUM ANALYZER 1.8nF FB* 120nH 22pF 270 0.1F DUT 237 0.1F 28
03199-C-054
0.1F
237 28 1:1
50 IN
INH LMD
50
0.1F
*FERRITE BEAD
Figure 54. Distortion
NETWORK ANALYZER
50 OUT
50 IN 50
1.8nF FB* 120nH 22pF 0.1F *FERRITE BEAD
270 237 28 50 1:1
0.1F
INH LMD
0.1F DUT
237 28
03199-C-055
0.1F
Figure 55. S11 Measurements
Rev. C | Page 16 of 32
AD8331/AD8332 THEORY OF OPERATION
OVERVIEW
The following discussion applies to all part numbers. Figure 56 and Figure 1 are functional block diagrams of the AD8331 and AD8332, respectively.
LON LOP VIP VIN
4 5 7 8
60 50 MODE = HI (WHERE AVAILABLE) HILO = HI 40
GAIN (dB)
VPOS
14
VCM
11
HILO
19
30 MODE = LO 20
VPSL 3
AD8331
COML 6 INH LMD
2
VMID
3.5dB/ 15.5dB
LNA
1
G = -48dB to 0dB
+21dB
VGA
POST AMP1
15 16
VOH VOL
10 HILO = LO 0
03199-C-058
LNA BIAS (VMID ) GAIN
10 20
GAIN INT
BIAS AND INTERPOLATOR
CLAMP
9
MODE
-10
03199-C-056
0
0.2
0.4
0.6 VGAIN (V)
0.8
1.0
1.1
17
19
18
12
COMM
COMM ENBL
ENBV
RCLMP
Figure 58. Gain Control Characteristics
Figure 56. Functional Block Diagram -- AD8331
Each channel contains an LNA that provides user-adjustable input impedance termination, a differential X-AMP VGA, and a programmable gain postamplifier with adjustable output voltage limiting. Figure 57 shows a simplified block diagram.
LON PREAMPLIFIER 19dB INH LMD + LNA - VOL VIN X-AMP VGA [(-48 to 0) + 21] dB POSTAMP 3.5dB/15.5dB VOH
When MODE is set high, (where available):
GAIN (dB) = - 50 dB V x VGAIN + 45.5 dB, (HILO = LO ) GAIN (dB) = - 50 dB V x VGAIN + 57.5 dB, (HILO = HI )
(
)
(3) (4)
(
)
or
LOP
VIP RCLMP
BIAS (VMID)
GAIN INTERFACE*
BIAS AND INTERPOLATOR*
VMID
CLAMP*
GAIN
VCM *SHARED BETWEEN CHANNELS
HILO
03199-B-057
The LNA converts a single-ended input to a differential output with a voltage gain of 19 dB. When only one output is used, the gain is 13 dB. The inverting output is used for active input impedance termination. Each of the LNA outputs is capacitively coupled to a VGA input. The VGA consists of an attenuator with a range of 48 dB followed by an amplifier with 21 dB of gain, for a net gain range of -27 dB to +21 dB. The X-AMP gain-interpolation technique results in low gain error and uniform bandwidth, and differential signal paths minimize distortion. The final stage is a logic programmable amplifier with gains of 3.5 dB or 15.5 dB. The LO and HI gain modes are optimized for 12-bit and 10-bit A/D converter applications, in terms of output-referred noise and absolute gain range. Output voltage limiting may be programmed by the user.
Figure 57. Simplified Block Diagram
The linear-in-dB gain control interface is trimmed for slope and absolute accuracy. The overall gain range is 48 dB, extending from -4.5 dB to +43.5 dB or from +7.5 dB to +55.5 dB, depending on the setting of the HILO pin. The slope of the gain control interface is 50 dB/V, and the gain control range is 40 mV to 1 V, leading to the following expressions for gain:
LOW NOISE AMPLIFIER (LNA)
Good noise performance relies on a proprietary ultralow noise preamplifier at the beginning of the signal chain, which minimizes the noise contribution in the following VGA. Active impedance control optimizes noise performance for applications that benefit from input matching.
GAIN (dB) = 50 (dB V ) x VGAIN - 6.5 dB, (HILO = LO ) (1) or GAIN (dB) = 50 (dB V ) x VGAIN + 5.5 dB, (HILO = HI ) (2 ) The gain characteristics are shown in Figure 58.
Rev. C | Page 17 of 32
AD8331/AD8332
A simplified schematic of the LNA is shown in Figure 59. INH is capacitively coupled to the source. An on-chip bias generator centers the output dc levels at 2.5 V and the input voltages at 3.25 V. A capacitor CLMD of the same value as the input coupling capacitor CINH is connected from the LMD pin to ground.
CFB LOP RFB VPOS LON
CFB is needed in series with RFB, since the dc levels at Pins LON and INH are unequal. Expressions for choosing RFB in terms of RIN and for choosing CFB are found in the Applications section. CSH and the ferrite bead enhance stability at higher frequencies where the loop gain declines and prevents peaking. Frequency response plots of the LNA are shown in Figure 19 and Figure 20. The bandwidth is approximately 130 MHz for matched input impedances of 50 to 200 and declines at higher source impedances. The unterminated bandwidth (RFB = ) is approximately 80 MHz. Each output can drive external loads as low as 100 in addition to the 100 input impedance of the VGA (200 differential). Capacitive loading up to 10 pF is permissible. All loads should be ac-coupled. Typically, Pin LOP output is used as a singleended driver for auxiliary circuits, such as those used for Doppler mode ultrasound imaging, and Pin LON drives RFB. Alternatively, a differential external circuit can be driven from the two outputs, in addition to the active feedback termination. In both cases, important stability considerations discussed in the Applications section should be carefully observed. The impedance at each LNA output is 5 . A 0.4 dB reduction in open-circuit gain results when driving the VGA, and 0.8 dB with an additional 100 load at the output. The differential gain of the LNA is 6 dB higher. If the load is less than 200 on either side, a compensating load is recommended on the opposite output.
I0
I0
CINH CSH RS
INH Q1 Q2
LMD CLMD
I0
I0
03199-C-059
Figure 59. Simplified LNA Schematic
The LNA supports differential output voltages as high as 5 V p-p with positive and negative excursions of 1.25 V, about a common-mode voltage of 2.5 V. Since the differential gain magnitude is 9, the maximum input signal before saturation is 275 mV or 550 mV p-p. Overload protection ensures quick recovery time from large input voltages. Since the inputs are capacitively coupled to a bias voltage near midsupply, very large inputs can be handled without interacting with the ESD protection. Low value feedback resistors and the current-driving capability of the output stage allow the LNA to achieve a low inputreferred voltage noise of 0.74 nV/Hz. This is achieved with a modest current consumption of 10 mA per channel (50 mW). On-chip resistor matching results in precise gains of 4.5 per side (9 differential), critical for accurate impedance control. The use of a fully differential topology and negative feedback minimizes distortion. Low HD2 is particularly important in second harmonic ultrasound imaging applications. Differential signaling enables smaller swings at each output, further reducing third order distortion.
LNA Noise
The input-referred voltage noise sets an important limit on system performance. The short-circuit input voltage noise of the LNA is 0.74 nV/Hz or 0.82 nV/Hz (at maximum gain), including the VGA noise. The open-circuit current noise is 2.5 pA/Hz. These measurements, taken without a feedback resistor, provide the basis for calculating the input noise and noise figure performance of the configurations in Figure 60. Figure 61 and Figure 62 are simulations extracted from these results, and the 4.1 dB NF measurement with the input actively matched to a 50 source. Unterminated (RFB = ) operation exhibits the lowest equivalent input noise and noise figure. Figure 61 shows the noise figure versus source resistance, rising at low RS, where the LNA voltage noise is large compared to the source noise, and again at high RS due to current noise. The VGA's input-referred voltage noise of 2.7 nV/Hz is included in all of the curves.
Active Impedance Matching
The LNA supports active impedance matching through an external shunt feedback resistor from Pin LON to Pin INH. The input resistance RIN is given by Equation 5, where A is the single-ended gain of 4.5, and 6 k is the unterminated input impedance.
R IN = 6 k x R FB R FB 6 k = 1+ A 33 k + R FB
(5)
Rev. C | Page 18 of 32
AD8331/AD8332
UNTERMINATED RIN RS VIN + - RESISTIVE TERMINATION RIN RS VIN + - RS VOUT VOUT
ACTIVE IMPEDANCE MATCH -RS = RIN RFB R
IN
RS VIN + - RFB 1 + 4.5
03199-C-060
VOUT
The primary purpose of input impedance matching is to improve the system transient response. With resistive termination, the input noise increases due to the thermal noise of the matching resistor and the increased contribution of the LNA's input voltage noise generator. With active impedance matching, however, the contributions of both are smaller than they would be for resistive termination by a factor of 1/(1 + LNA Gain). Figure 61 shows their relative noise figure (NF) performance. In this graph, the input impedance has been swept with RS to preserve the match at each point. The noise figures for a source impedance of 50 are 7.1 dB, 4.1 dB, and 2.5 dB, respectively, for the resistive, active, and unterminated configurations. The noise figures for 200 are 4.6 dB, 2.0 dB, and 1.0 dB, respectively. Figure 62 is a plot of the NF versus RS for various values of RIN, which is helpful for design purposes. The plateau in the NF for actively matched inputs mitigates source impedance variations. For comparison purposes, a preamp with a gain of 19 dB and noise spectral density of a 1.0 nV/Hz, combined with a VGA with 3.75 nV/Hz, would yield a noise figure degradation of approximately 1.5 dB (for most input impedances), significantly worse than the AD8332 performance. The equivalent input noise of the LNA is the same for singleended and differential output applications. The LNA noise figure improves to 3.5 dB at 50 without VGA noise, but this is exclusive of noise contributions from other external circuits connected to LOP. A series output resistor is usually recommended for stability purposes, when driving external circuits on a separate board (see the Applications section). In low noise applications, a ferrite bead is even more desirable.
RIN =
Figure 60. Input Configurations
7 INCLUDES NOISE OF VGA 6 RESISTIVE TERMINATION (RS = RIN)
NOISE FIGURE (dB)
5
4 3
ACTIVE IMPEDANCE MATCH
2 UNTERMINATED SIMULATION 0 50 100 RS () 1k
03199-C-061
1
VARIABLE GAIN AMPLIFIER
The differential X-AMP VGA provides precise input attenuation and interpolation. It has a low input-referred noise of 2.7 nV/Hz and excellent gain linearity. A simplified block diagram is shown in Figure 63.
Figure 61. Noise Figure vs. RS for Resistive, Active Matched, and Unterminated Inputs
7 INCLUDES NOISE OF VGA 6
GAIN
GAIN INTERPOLATOR (BOTH CHANNELS) POST-AMP
NOISE FIGURE (dB)
5 4
RIN = 50
gm VIP 6dB R VIN 48dB 2R
70 3 2 RFB =
03199-C-081
100 200
SIMULATION 0 50 100 RS ()
1k
POST-AMP
Figure 63. Simplified VGA Schematic Figure 62. Noise Figure vs. RS for Various Fixed Values of RIN, Actively Matched
Rev. C | Page 19 of 32
03199-C-063
1
AD8331/AD8332
X-AMP VGA
The input of the VGA is a differential R-2R ladder attenuator network, with 6 dB steps per stage and a net input impedance of 200 differential. The ladder is driven by a fully differential input signal from the LNA and is not intended for single-ended operation. LNA outputs are ac-coupled to reduce offset and isolate their common-mode voltage. The VGA inputs are biased through the ladder's center tap connection to VCM, which is typically set to 2.5 V and is bypassed externally to provide a clean ac ground. The signal level at successive stages in the input attenuator falls from 0 dB to -48 dB, in 6 dB steps. The input stages of the X-AMP are distributed along the ladder, and a biasing interpolator, controlled by the gain interface, determines the input tap point. With overlapping bias currents, signals from successive taps merge to provide a smooth attenuation range from 0 dB to -48 dB. This circuit technique results in excellent, linear-in-dB gain law conformance and low distortion levels and deviates 0.2 dB or less from ideal. The gain slope is monotonic with respect to the control voltage and is stable with variations in process, temperature, and supply. The X-AMP inputs are part of a gain-of-12 feedback amplifier, which completes the VGA. Its bandwidth is 150 MHz. The input stage is designed to reduce feedthrough to the output and ensure excellent frequency response uniformity across gain setting (see Figure 8 and Figure 9). Gain control response time is less than 750 ns to settle within 10% of the final value for a change from minimum to maximum gain.
VGA Noise
In a typical application, a VGA compresses a wide dynamic range input signal to within the input span of an ADC. While the input-referred noise of the LNA limits the minimum resolvable input signal, the output-referred noise, which depends primarily on the VGA, limits the maximum instantaneous dynamic range that can be processed at any one particular gain control voltage. This limit is set in accordance with the quantization noise floor of the ADC. Output and input-referred noise as a function of VGAIN are plotted in Figure 21 and Figure 23 for the short-circuited input condition. The input noise voltage is simply equal to the output noise divided by the measured gain at each point in the control range. The output-referred noise is flat over most of the gain range, since it is dominated by the fixed output-referred noise of the VGA. Values are 48 nV/Hz in LO gain mode and 178 nV/Hz in HI gain mode. At the high end of the gain control range, the noise of the LNA and source prevail. The input-referred noise reaches its minimum value near the maximum gain control voltage, where the input-referred contribution of the VGA becomes very small. At lower gains, the input-referred noise, and thus noise figure, increases as the gain decreases. The instantaneous dynamic range of the system is not lost, however, since the input capacity increases with it. The contribution of the ADC noise floor has the same dependence as well. The important relationship is the magnitude of the VGA output noise floor relative to that of the ADC. With its low output-referred noise levels, these devices ideally drive low-voltage ADCs. The converter noise floor drops 12 dB for every 2 bits of resolution and drops at lower input full-scale voltages and higher sampling rates. ADC quantization noise is discussed in the Applications section. The preceding noise performance discussion applies to a differential VGA output signal. Although the LNA noise performance is the same in single-ended and differential applications, the VGA performance is not. The noise of the VGA is significantly higher in single-ended usage, since the contribution of its bias noise is designed to cancel in the differential signal. A transformer can be used with single-ended applications when low noise is desired.
Gain Control
Position along the VGA attenuator is controlled by a singleended analog control voltage, VGAIN, with an input range of 40 mV to 1.0 V. The gain control scaling is trimmed to a slope of 50 dB/V (20 mV/dB). Values of VGAIN beyond the control range saturate to minimum or maximum gain values. Both channels of the AD8332 are controlled from a single gain interface to preserve matching. Gain can be calculated using Equations 1 and 2. Gain accuracy is very good since both the scaling factor and absolute gain are factory trimmed. The overall accuracy relative to the theoretical gain expression is 1 dB for variations in temperature, process, supply voltage, interpolator gain ripple, trim errors, and tester limits. The gain error relative to a best-fit line for a given set of conditions is typically 0.2 dB. Gain matching between channels is better than 0.1 dB (see Figure 7, which shows gain errors in the center of the control range). When VGAIN < 0.1 or > 0.95, gain errors are slightly greater. The gain slope may be inverted, as shown in Figure 58 (available in most versions). The gain drops with a slope of -50 dB/V across the gain control range from maximum to minimum gain. This slope is useful in applications, such as automatic gain control, where the control voltage is proportional to the measured output signal amplitude. The inverse gain mode is selected by setting the MODE pin HI.
Rev. C | Page 20 of 32
AD8331/AD8332
Gain control noise is a concern in very low noise applications. Thermal noise in the gain control interface can modulate the channel gain. The resultant noise is proportional to the output signal level and usually only evident when a large signal is present. Its effect is observable only in LO gain mode, where the noise floor is substantially lower. The gain interface includes an on-chip noise filter, which reduces this effect significantly at frequencies above 5 MHz. Care should be taken to minimize noise impinging at the GAIN input. An external RC filter may be used to remove VGAIN source noise. The filter bandwidth should be sufficient to accommodate the desired control bandwidth.
+ Gm2 VOH Gm1 F2
VCM
F1
Gm2 - Gm1 VOL
03199-B-064
Figure 64. Postamplifier Block Diagram
Common-Mode Biasing
An internal bias network connected to a midsupply voltage establishes common-mode voltages in the VGA and postamp. An externally bypassed buffer maintains the voltage. The bypass capacitors form an important ac ground connection, since the VCM network makes a number of important connections internally, including the center tap of the VGA's differential input attenuator, the feedback network of the VGA's fixed gain amplifier, and the feedback network of the postamplifier in both gain settings. For best results, use a 1 nF and a 0.1 F capacitor in parallel, with the 1 nF nearest to Pin VCM. Separate VCM pins are provided for each channel. For dc-coupling to a 3 V ADC, the output common-mode voltage is adjusted to 1.5 V by biasing the VCM pin.
Although the quantization noise floor of an ADC depends on a number of factors, the 48 nV/Hz and 178 nV/Hz levels are well suited to the average requirements of most 12-bit and 10-bit converters, respectively. An additional technique, described in the Applications section, can extend the noise floor even lower for possible use with 14-bit ADCs.
Output Clamping
Outputs are internally limited to a level of 4.5 V p-p differential when operating at a 2.5 V common-mode voltage. The postamp implements an optional output clamp engaged through a resistor from RCLMP to ground. Table shows a list of recommended resistor values. Output clamping can be used for ADC input overload protection, if needed, or postamp overload protection when operating from a lower common-mode level, such as 1.5 V. The user should be aware that distortion products increase as output levels approach the clamping levels and should adjust the clamp resistor accordingly. Also, see the Applications section. The accuracy of the clamping levels is approximately 5% in LO or HI mode. Figure 65 illustrates the output characteristics for a few values of RCLMP.
5.0 4.5 4.0 8.8k 3.5 3.5k VOH, VOL (V) 3.0 2.5 2.0 1.5 1.0 0.5 0 -3 -2 -1 0 VINH (V) 1 2 3
03199-C-065
POSTAMPLIFIER
The final stage has a selectable gain of 3.5 dB or 15.5 dB, set by the logic Pin HILO. These correspond to linear gains of 1.5 or 6. A simplified block diagram of the postamplifier is shown in Figure 64. Separate feedback attenuators implement the two gain settings. These are selected in conjunction with an appropriately scaled input stage to maintain a constant 3 dB bandwidth between the two gain modes (~150 MHz). The slew rate is 1200 V/s in HI gain mode and 300 V/s in LO gain mode. The feedback networks for HI and LO gain modes are factory trimmed to adjust the absolute gains of each channel.
RCLMP =
Noise
The topology of the postamplifier provides constant inputreferred noise with the two gain settings and variable outputreferred noise. The output-referred noise in HI gain mode increases (with gain) by four. This setting is recommended when driving converters with higher noise floors. The extra gain boosts the output signal levels and noise floor appropriately. When driving circuits with lower input noise floors, the LO gain mode optimizes the output dynamic range.
RCLMP = 1.86k
Figure 65. Output Clamping Characteristics
Rev. C | Page 21 of 32
AD8331/AD8332 APPLICATIONS
LNA - EXTERNAL COMPONENTS
The LMD pin (connected to the bias circuitry) must be bypassed to ground, and signal source to the INH pin capacitively coupled using 2.2 nF to 0.1 F capacitors (see Figure 66). The unterminated input impedance of the LNA is 6 k. The user may synthesize any LNA input resistance between 50 and 6 k. RFB is calculated according to Equation 6 or selected from Table .
R FB = 33 k x (R IN ) 6 k - (R IN )
1 2 +5V 3 4 5 6 1nF 0.1F 7 8 9 1nF 10 1nF 11 12 13 14 INH2 VPS2 LON2 LOP2 COM2 VIP2 VIN2 VCM2 GAIN RCLMP VOH2 VOL2 COMM CLMD 0.1F LMD2 LMD1 INH1 VPS1 LON1 LOP1 COM1 VIP1 VIN1 VCM1 HILO ENB VOH1 VOL1 VPSV 28 27 26 25 24 23 22 0.1F 21 20 19 18 17 16 15 1nF 1nF 0.1F 5V 5V CFB* RFB * LNA OUT CSH* 1n F 5V 0.1 F FB LNA SOURCE 0.1F
VGAIN
(6)
Table 3. LNA External Component Values for Common Source Impedances
RIN () 50 75 100 200 500 6k RFB (Nearest STD 1% Value, ) 280 412 562 1.13k 3.01k CSH (pF) 22 12 8 1.2 None None
0.1F
* *
VGA OUT VGA OUT 0.1F 5V
03199-C-066
*SEE TEXT
Figure 66. Basic Connections for a Typical Channel (AD8332 Shown)
TO EXT CIRCUIT
When active input termination is used, a 0.1 F capacitor (CFB) is required to isolate the input and output bias voltages of the LNA. The shunt input capacitor, CSH, reduces gain peaking at higher frequencies where the active termination match is lost due to the HF gain roll-off of the LNA. Suggested values are shown in Table ; for unterminated applications, reduce the capacitor value by half. When a long trace to Pin INH is unavoidable, or if both LNA outputs drive external circuits, a small ferrite bead (FB) in series with Pin INH preserves circuit stability with negligible effect on noise. The bead shown is 75 at 100 MHz (Murata BLM21 or equivalent). Other values may prove useful. Figure 67 shows the interconnection details of the LNA output. Capacitive coupling between LNA outputs and the VGA inputs is required because of differences in their dc levels and to eliminate the offset of the LNA. Capacitor values of 0.1 F are recommended. There is 0.4 dB loss in gain between the LNA output and the VGA input due to the 5 output resistance. Additional loading at the LOP and LON outputs will affect LNA gain.
LNA CSH
5 LON
VIP
50 100
VCM
5
LOP VIN
100 50
TO EXT CIRCUIT
Figure 67. Interconnections of the LNA and VGA
Both LNA outputs are available for driving external circuits. Pin LOP should be used in those instances when a single-ended LNA output is required. The user should be aware of stray capacitance loading of the LNA outputs, in particular LON. The LNA can drive 100 in parallel with 10 pF. If an LNA output is routed to a remote PC board, it will tolerate a load capacitance up to 100 pF with the addition of a 49.9 series resistor or ferrite 75 /100 MHz bead.
Rev. C | Page 22 of 32
03199-C-067
AD8331/AD8332
Gain Input
Pin GAIN is common to both channels of the AD8332. The input impedance is nominally 10 M and a bypass capacitor from 100 pF to1 nF is recommended. Parallel connected devices may be driven by a common voltage source or DAC. Decoupling should take into account any bandwidth considerations of the drive waveform, using the total distributed capacitance. If gain control noise in LO gain mode becomes a factor, maintaining 15 nV/Hz noise at the GAIN pin will ensure satisfactory noise performance. Internal noise prevails below 15 nV/Hz at the GAIN pin. Gain control noise is negligible in HI gain mode.
Logic Inputs--ENB, MODE, and HILO
The input impedance of all enable pins is nominally 25 k and may be pulled up to 5 V (a pull-up resistor is recommended) or driven by any 3 V or 5 V logic families. The enable pins perform a power-down function, when disabled, the VGA outputs are near ground. Multiple devices may be driven from a common source. Consult the pin-function tables for circuit functions controlled by the enable pins. Pin HILO is compatible with 3 V or 5 V CMOS logic families. It is either connected to ground or pulled up to 5 V, depending on the desired gain range and output noise.
Optional Output Voltage Limiting
The RCLMP pin provides the user with a means to limit the output voltage swing when used with loads that have no provisions for prevention of input overdrive. The peak-to-peak limited voltage is adjusted by a resistor to ground, and Table lists several voltage levels and the corresponding resistor value. Unconnected, the default limiting level is 4.5 V p-p. Note that third harmonic distortion will increase as waveform amplitudes approach clipping. For lowest distortion, the clamp level should be set higher than the converter input span. A clamp level of 1.5 V p-p is recommended for a 1 V p-p linear output range, 2.7 V p-p for a 2 V p-p range, or 1 V p-p for a 0.5 V p-p operation. The best solution will be determined experimentally. Figure 69 shows third harmonic distortion as a function of the limiting level for a 2 V p-p output signal. A wider limiting level is desirable in HI gain mode.
-20 VGAIN = 0.75V -30
VCM Input
The common-mode voltage of Pins VCM, VOL, and VOH defaults to 2.5 Vdc. With output ac-coupled applications, the VCM pin will be unterminated; however, it must still be bypassed in close proximity for ac grounding of internal circuitry. The VGA outputs may be dc connected to a differential load, such as an ADC. Common-mode output voltage levels between 1.5 V and 3.5 V may be realized at Pins VOH and VOL by applying the desired voltage at Pin VCM. DC-coupled operation is not recommended when driving loads on a separate PC board. The voltage on the VCM pin is sourced by an internal buffer with an output impedance of 30 and a 2 mA default output current (see Figure 68). If the VCM pin is driven from an external source, its output impedance should be <<30 and its current drive capability should be >>2 mA. If the VCM pins of several devices are connected in parallel, the external buffer should be capable of overcoming their collective output currents. When a common-mode voltage other than 2.5 V is used, a voltage-limiting resistor, RCLMP, is needed to protect against overload.
2mA MAX INTERNAL CIRCUITRY RO << 30 30 VCM 100pF AC GROUNDING FOR INTERNAL CIRCUITRY NEW VCM
-40
HD3 (dBc)
-50 HILO = LO -60 HILO = HI
03199-C-069
-70
03199-B-068
0.1F
-80 1.5
2.0
2.5 3.0 3.5 4.0 CLAMP LIMIT LEVEL (V p-p)
4.5
5.0
Figure 68. VCM Interface
Figure 69. HD3 vs. Clamping Level for 2 V p-p Differential Input
Rev. C | Page 23 of 32
AD8331/AD8332
Table 4. Clamp Resistor Values
Clamp Level (V p-p) 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.4 Clamp Resistor Value (k) HILO = LO HILO = HI 1.21 2.74 2.21 4.75 4.02 7.5 6.49 11 9.53 16.9 14.7 26.7 23.2 49.9 39.2 100 73.2
The relative noise and distortion performance of the two gain modes can be compared in Figure 21 and Figure 27 through Figure 37. The 48 nV/Hz noise floor of the LO gain mode is suited to converters with higher sampling rates or resolutions (such as 12 bits). Both gain modes can accommodate ADC fullscale voltages as high as 4 V p-p. Since distortion performance remains favorable for output voltages as high as 4 V p-p (see Figure 32), it is possible to lower the output-referred noise even further by using a resistive attenuator (or transformer) at the output. The circuit in Figure 71 has an output full-scale range of 2 V p-p, a gain range of -10.5 dB to +37.5 dB, and an output noise floor of 24 nV/Hz, making it suitable for some 14-bit ADC applications.
4V p-p DIFF, 48n V/ HZ VOH VOL 187 187 2:1 374 2V p-p DIFF, 24n V/ HZ LPF
03199-C-071
Output Filtering and Series Resistor Requirements
To ensure stability at the high end of the gain control range, series resistors or ferrite beads are recommended for the outputs when driving large capacitive loads, or circuits on other boards,. These components can be part of the external noise filter. Recommended resistor values are 84.5 for LO gain mode and 100 for HI gain mode (see Figure 66) and are placed near Pins VOH and VOL. Lower value resistors are permissible for applications with nearby loads or with gains less than 40 dB. Lower values are best selected empirically. An antialiasing noise filter is typically used with an ADC. Filter requirements are application dependent. When the ADC resides on a separate board, the majority of filter components should be placed nearby to suppress noise picked up between boards and mitigates charge kickback from the ADC inputs. Any series resistance beyond that required for output stability should be placed on the ADC board. Figure 70 shows a second order low-pass filter with a bandwidth of 20 MHz. The capacitor is chosen in conjunction with the 10 pF input capacitance of the ADC.
OPTIONAL BACKPLANE 84.5 84.5
0.1F 0.1F 1.5H
ADC AD6644
Figure 71. Adjusting the Noise Floor for 14-Bit ADCs
OVERLOAD
These devices respond gracefully to large signals that overload its input stage and to normal signals that overload the VGA when the gain is set unexpectedly high. Each stage is designed for clean-limited overload waveforms and fast recovery when gain setting or input amplitude is reduced. Signals larger than 275 mV at the LNA input are clipped to 5 V p-p differential prior to the input of the VGA. Figure 44 shows the response to a 1 V p-p input burst. The symmetric overload waveform is important for applications, such as CW Doppler ultrasound, where the spectrum of the LNA outputs during overload is critical. The input stage is also designed to accommodate signals as high as 2.5 V without triggering the slow-settling ESD input protection diodes. Both stages of the VGA are susceptible to overload. Postamp limiting is more common and results in the clean-limited output characteristics found in Figure 45. Under more extreme conditions, the X-AMP will overload, causing the minor glitches evident in Figure 46. Recovery is fast in all cases. The graph in Figure 72 summarizes the combinations of input signal and gain that lead to the different types of overload.
158 158 18pF ADC
1.5H
Figure 70. 20 MHz Second-Order Low-Pass Filter
DRIVING ADCS
The output drive will accommodate a wide range of ADCs. The noise floor requirements of the VGA will depend on a number of application factors, including bit resolution, sampling rate, full-scale voltage, and the bandwidth of the noise/antialias filter. The output noise floor and gain range can be adjusted by selecting HI or LO gain mode.
Rev. C | Page 24 of 32
AD8331/AD8332
POSTAMP OVERLOAD 43.5 15mV X-AMP OVERLOAD 25mV 56.5 POSTAMP OVERLOAD 4mV X-AMP OVERLOAD 25mV
LAYOUT, GROUNDING, AND BYPASSING
41dB
29dB
GAIN (dB)
LNA OVERLOAD
LNA OVERLOAD
LO GAIN MODE
GAIN (dB)
24.5dB
24.5dB HI GAIN MODE
Due to their excellent high frequency characteristics, these devices are sensitive to their PCB environment. Realizing expected performance requires attention to detail critical to good high speed board design. A multilayer board with power and ground plane is recommended, and unused area in the signal layers should be filled with ground. The multiple power and ground pins provide robust power distribution to the device and must all be connected. The power supply pins should each be with multiple values of high frequency ceramic chip capacitors to maintain low impedance paths to ground over a wide frequency range. These should have capacitance values of 0.01 F to 0.1 F in parallel with 100 pF to 1 nF, and be placed as close as possible to the pins. The LNA power pins should be decoupled from the VGA using ferrite beads. Together with the decoupling capacitors, ferrite beads help eliminate undesired high frequencies without reducing the headroom, as do small value resistors. Several critical LNA areas require special care. The LON and LOP output traces must be as short as possible before connecting to the coupling capacitors connected to Pins VIN and VIP. RFB must be placed nearby the LON pin as well. Resistors must be placed as close as possible to the VGA output pins VOL and VOH to mitigate loading effects of connecting traces. Values are discussed in the section entitled Output Filtering and Series Resistor Requirements. Signal traces must be short and direct to avoid parasitic effects. Wherever there are complementary signals, symmetrical layout should be employed to maintain waveform balance. PCB traces should be kept adjacent when running differential signals over a long distance.
-4.5 1m
10m
0.1
.275
1
7.5 1m
INPUT AMPLITUDE (V)
10m 0.1 0.275 INPUT AMPLITUDE (V)
1
Figure 72. Overload Gain and Signal Conditions
The previously mentioned clamp interface controls the maximum output swing of the postamp and its overload response. When no RCLMP resistor is provided, this level defaults to near 4.5 V p-p differential to protect outputs centered at a 2.5 V common mode. When other common-mode levels are set through the VCM pin, the value of RCLMP should be chosen for graceful overload. A value of 8.3 k or less is recommended for 1.5 V or 3.5 V common-mode levels (7.2 k for HI gain mode). This limits the output swing to just above 2 V p-p diff.
OPTIONAL INPUT OVERLOAD PROTECTION.
Applications in which high transients are applied to the LNA input may benefit from the use of clamp diodes. A pair of backto-back Schottky diodes can reduce these transients to manageable levels. Figure 73 illustrates how such a diodeprotection scheme may be connected.
OPTIONAL SCHOTTKY OVERLOAD CLAMP FB 3
COMM 0.1F RSH CSH CFB RFB 3 4 VPS LON 2 INH ENBL
20 19
03199-C-072
2
1 BAS40-04
03199-C-072
MULTIPLE INPUT MATCHING
Matching of multiple sources with dissimilar impedances can be accomplished as shown in the circuit of Figure 75. A relay and low supply voltage analog switch may be used to select between multiple sources and their associated feedback resistors. An ADG736 dual SPDT switch is shown in this example; however, multiple switches are also available and users are referred to the Analog Devices Selection Guide for switches and multiplexers.
Figure 73. Input Overload Clamping
When selecting overload protection, the important parameters are forward and reverse voltages and trr (or rr.). The Infineon BAS40 series shown in Figure 73 has a rr of 100 ps and VF of 310 mV at 1 mA. Many variations of these specifications can be found in vendor catalogs.
DISABLING THE LNA
Where accessible, connection of the LNA enable pin to ground will power down the LNA, resulting in a current reduction of about half. In this mode, the LNA input and output pins may be left unconnected, however the power must be connected to all the supply pins for the disabling circuit to function. Figure 74 illustrates the connections using an AD8331 as an example.
Rev. C | Page 25 of 32
AD8331/AD8332
NC 1 LMD COMM 20
MEASUREMENT CONSIDERATIONS
Figure 51 through Figure 55 show typical measurement configurations and proper interface values for measurements with 50 conditions. Short-circuit input noise measurements are made using Figure 53. The input-referred noise level is determined by dividing the output noise by the numerical gain between Point A and Point B and accounting for the noise floor of the spectrum analyzer. The gain should be measured at each frequency of interest and with low signal levels since a 50 load is driven directly. The generator is removed when noise measurements are made.
AD8331
NC 2 INH ENBL 19
CFB 0.018F +5V 3 VPS ENBV 18 +5V
NC
4
LON
COMM
17
NC
5
LOP
VOL
16
VOUT 6 COML VOH 15
ULTRASOUND TGC APPLICATION
The AD8332 ideally meets the requirements of medical and industrial ultrasound applications. The TGC amplifier is a key subsystem in such applications, since it provides the means for echolocation of reflected ultrasound energy. Figure 76 through Figure 78 are schematics of a dual, fully differential system using the AD8332 and AD9238 12-bit high speed ADC with conversion speeds as high as 65 MSPS. In this example, the VGA outputs are dc-coupled, using the reference output of the ADC and a level shifter to center the commonmode output voltage to match that of the converter. Consult the data sheet of the converter to determine whether external CMV biasing is required. AC coupling is recommended if the CMV of the VGA and ADC are widely disparate. Using the circuit shown, and a high speed ADC FIFO evaluation kit connected to a laptop PC, an FFT can be performed on the AD8332. With the on-board clock of 20 MHz, and minimal low-pass filtering, and both channels driven with a 1 MHz filtered sine wave, the THD is -75 dB, noise floor -93 dB and HD2 -83 dB.
0.1F
7
VIP
VPOS
14
+5V
VIN 0.1F 8 VIN HILO 13 HILO
MODE
9
MODE
CLMP
12 RCLMP
GAIN
10
GAIN
VCM
11
VCM
03199-C-074
Figure 74. Disabling the LNA
ADG736
SELECTRFB
1.13k
280
18nF 200
LON 5 INH
03199-C-075
LMD
50 0.1F
LNA
5
LOP
AD8332
Figure 75. Accommodating Multiple Sources
Rev. C | Page 26 of 32
AD8331/AD8332
S3 EIN2 TP5 C50 0.1F TP3 (RED) TB1 +5V + TP4 (BLACK) TB2 GND C46 1F CFB2 18nF
AD8332ARU
1 C49 0.1F 2 LMD2 LMD1 28 C70 0.1F INH2 INH1 27 JP6 IN1 3 C74 1nF 4 LON2 LON1 VPS2 VPS1 26 +5VLNA 25 RFB1 274 C79 22 PF TP6 L13 120nH FB C60 0.1F
+5V
L12 120nH FB C80 22PF +5VLNA RFB2 274 C41 0.1F
JP5 IN2
S1 EIN1
CFB1 18nF
L7 120nH FB +5VGA
L6 120nH FB +5VLNA
5
LOP2
LOP1
24
0.1F 7
C51 0.1F
C53 0.1F
6
COM2
COM1
23
C42 0.1F
C59 0.1F
VREF
3
7
AD8541
6 4 VCM1 JP13 JP14 C48 0.1F C78 1nF 9 8
VIP2
VIP1
22
2
VIN2
VIN1
21 VCM1
C71 1nF
VCM2
VCM1
20 C77 1nF C43 0.1F +5VGA HI GAIN JP10 LO GAIN
R23 2k
R22 1k
VCM 10 C83 1nF 11 R3 (RCLMP) C69 0.1F R27 100 L11 120nH FB 13 C68 1nF 12 VOH2 VOH1 17 CLMP 19 HILO
TP2 GAIN TP7 GND
GAIN
+5VGA 18 ENB ENABLE JP16 DISABLE
OPTIONAL 4-POLE LOW-PASS FILTER VIN+B C66 SAT VIN-B L19 SAT C67 L20 SAT SAT L17 SAT
JP8 DC2H
R24 100 16 L9 120nH FB
JP9 C58 0.1F JP17 C56 0.1 F
OPTIONAL 4-POLE LOW-PASS FILTER L1 SAT L15 SAT C64 SAT L16 SAT VIN+A C65 SAT
C54 0.1F
VOL2
VOL1
L18 JP12 SAT
C55 0.1F JP7 DC2L
L10 120nH FB
14 COM VPSV
15
L8 120nF FB
L14 SAT
VIN-A +5VGA C45 0.1F
03199-C-076
R26 100 C85 1nF
R25 100 JP10
Figure 76. Schematic, TGC, VGA Section
Rev. C | Page 27 of 32
AD8331/AD8332
VR1 ADP3339AKC-3.3
+5V 3 IN 2 1 L4 120nH FB C44 1F +
+3.3VAVDD
L5 120nH FB
+3.3VCLK
C31
0.1F +3.3VADDIG
C30
C22 0.1F C2 10F 6.3V +
1 2
C21 1nF
ADCLK R11 100 R10 JP 2 0 SHARED REF Y N R14 4.7k R15 +3.3VADDIG 0
OUT GND
OUT TAB
0.1F
L3 120nH FB +3.3VAVDD C29
VIN+_A VIN-_A R12 1.5k C35 0.1F
R5 33
AGND VIN+_A VIN -_A AGND AVDD REFT_A REFB_A VREF SENSE REFB_B REFT_B AVDD AGND VIN -_B VIN+_B AGND AVDD CLK_B DCS DFS PDWN_B OEB_B DNC DNC D0_B D1_B D2_B DRGND DRVDD D3_B D4_B D5_B
AVDD CLK_A SHARED_REF MUX_SELECT PDWN_A OEB_A OTRA_A D11_A(MSB) D10_A D9_A
64 63 62 61 60 59 58 57 56 55 54 53
C61 18pF R4 C18 1.5k C17 1nF C33 0.1F 10F 6.3V + C40 0.1F TP 9 C32 + 0.1F C12 10F 6.3V C57 10nF R6 33
3 4 5 6
0.1F
L2 120nH FB
+3.3VDVDD
C1 0.1F
C52 10nF
7 8 9 10
OTR_A D11_A D10_A D9_A D8_A +3.3VADDIG C23 0.1F D7_A D6_A D5_A D4_A D3_A D2_A D1_A D0_A DNC DNC C13 1nF OTR_B D11_B D10_B D9_B D8_B D7_B D6_B C14 + 0.1F C11 10F 6.3V C25 1nF
C36 0.1F VREF C38 0.1F C34 10F 6.3V
C37 0.1F 1.5k C16 1.5k 0.1F R8 33 C15 1nF
12 13 14
U1 A/D CONVERTER AD9238
C39 10F
11
D8_A DRGND
DRVDD 52 D7_A D6_A D5_A D4_A D3_A D2_A D1_A D0_A DNC DNC DRVDD DRGND OTRB_B
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
VIN-B VIN+B +3.3VCLK R18 499 R16 5k R17 49.9 R19 499
JP 3
C62 18pF R7 33
15 16 17
S2 EXT CLOCK
C63 0.1F
C20 0.1F
C19 1nF
18 19
JP 11
20 21 22
R20 4.7k +3.3VCLK
R41 4.7k
ADCLK C86 0.1F + C47 10F 6.3V EXT 3 JP 4 2 1 INT
U5 74VHC04 5 6 9 U5 74VHC04 8 1 JP 1 U5 74VHC04 13 12 2 U5 74VHC04 3 4 1
DNC DNC R9 0 D0_B D1_B
23 24 25 26 27 28 29
ADCLK
U5 74VHC04 2
TP 12
4 1 VDD OE 20MHz 3 OUT GND 2
TP 13
D2_B
DATA CLK 3 D3_B D4_B D5_B
D11_B(MSB) D10_B D9_B D8_B D7_B D6_B
U6 SG-636PCE
30 31 32
SPARES
+3.3VADDIG
U5 74VHC04
C26 0.1F
C24 1nF
Figure 77. Converter Schematic
Rev. C | Page 28 of 32
03199-C-077
11
10
AD8331/AD8332
DATACLKA 19
22 x 4 1 2 RP 9 8 7
OTR_A D11_A D10_A
1 3 4 22 x 4 RP 10 6 5 8
20 U10 VCC 74VHC541 10 GND G2 18 2 Y1 A1 17 3 A2 Y2 16 4 A3 Y3 1 G1 5 6 7 8 9 A4 A5 A6 A7 A8 Y4 Y5 Y6 Y7 Y8 15 14 13 12 11
+3.3VDVDD
+ C3 0.1F C28 10F 6.3V
1 2 3 4 1
R40 22 2
22 x 4 8 RP 1
1 3 5 7 9 11 13
HEADER UP MALE NO SHROUD
4 6 8 10 12 14 16 18 20 22 24 26
8 7
7 6 5
22 x 4 RP2
8
D9_A D8_A D7_A D6_A
2 3 4
7 6 5
2 3 4 1 2
7 6 5
15 17 19 21 23 25 27 29 31 33 35 37 39
22 x 4 RP 3
8 7
+3.3VDVDD
1 U7 VCC 20 74VHC541 10 G2 GND 18 2 Y1 A1 3 17 A2 Y2 G1 4 5 6 7 8 9 A3 A4 A5 A6 A7 A8 Y3 Y4 Y5 Y6 Y7 Y8 16 15 14 13 12 11 C10 + 0.1F
3 4 1 2 22 x 4 RP 4
6 5
19 D5_A D4_A D3_A
4 5 22 x 4 RP 12 8 1 2 3 22 x 4 RP 11 8
C8 0.1F
C76 10F 6.3V
28 30 32 34 36 38 40
3 4
6 5
7 6
D2_A
1
D1_A D0_A DNC
4 2 3
7 6 5
SAM080UPM
DNC
+3.3VDVDD
20 U2 VCC G1 74VHC541 19 10 GND G2 2 18 Y1 A1 3 17 A2 Y2 4 16 A3 Y3 5 15 A4 Y4 6 14 A5 Y5 7 13 A6 Y6 8 12 A7 Y7 9 11 A8 Y8 1 42 + C7 0.1F + C9 0.1F C27 10F 6.3V
1 2 3 4 22 x 4 RP 6
41 43 45 47 49 51 53
HEADER UP MALE NO SHROUD
1
22 x 4 RP 13
8
44
22 x 4 RP 5 8 7 6 5 8
OTR_B D11_B
2 3 4
7 6 5
46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 SAM080UPM
D10_B D9_B D8_B D7_B D6_B D5_B
1 2 22 x 4 RP 14 7 8
1 2 3 4
3 4 1 22 x 4
6 5 8
7 6 5
55 57 59 61 63 65 67 69 71 73 75 77 79
03199-B-078
1
22 x 4 RP 7
8 7 6 5
+3.3VDVDD
RP 15
2 3
D4_B D3_B
2 3 4
7 6 5 22 x 4 RP 16 8
20 U3 VCC 74VHC541 19 10 G2 GND 18 2 A1 Y1 G1 3 4 5 6 7 8 9 A2 A3 A4 A5 A6 A7 A8 Y2 Y3 Y4 Y5 Y6 Y7 Y8 17
1
C4 0.1F
C5 0.1F
C6 0.1F
+
C75 10F 6.3V
4 1 22 x 4 RP 8
8
2 3
7 6 5
D2_B
1
16
4
D1_B D0_B DNC DNC
2 3 4 7 6 5
15 14 13 12 11 R39 22
DATACLK
Figure 78. Interface Schematic
Rev. C | Page 29 of 32
AD8331/AD8332 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD8331
LMD INH VPSL LON LOP COML VIP VIN MODE
1 2 3 4 5 6 7 8 9
PIN 1 IDENTIFIER
20 19 18
COMM ENBL ENBV COMM VOL VOH VPOS HILO RCLMP VCM
03199-C-079
AD8331
TOP VIEW (Not to Scale)
17 16 15 14 13 12 11
GAIN 10
Figure 79. 20-Lead QSOP
Table 5. 20-Lead QSOP (RQ PACKAGE)
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Name LMD INH VPSL LON LOP COML VIP VIN MODE GAIN VCM CLMP HILO VPOS VOH VOL COMM ENBV ENBL COMM Description LNA Signal Ground LNA Input LNA 5V Supply LNA Inverting Output LNA Noninverting Output LNA Ground VGA Noninverting Input VGA Inverting Input Gain Slope Logic Input Gain Control Voltage Common-Mode Voltage Output Clamping Level Gain Range Select (HI or LO) VGA 5 V Supply Noninverting VGA Output Inverting VGA Output VGA Ground VGA Enable LNA Enable VGA Ground
Rev. C | Page 30 of 32
AD8331/AD8332
AD8332
LMD2 INH2 VPS2 LON2 LOP2 COM2 VIP2 VIN2 VCM2 GAIN
1 2 3 4 5 6 7 8 9 10
PIN 1 IDENTIFIER
28 LMD1 27 INH1 26 VPS1 25 LON1 24 LOP1
32 31 30 29 28 27 26 25
LOP1 COM1 VIP1 VIN1 VCM1 HILO ENBL ENBV
AD8332
TOP VIEW (Not to Scale)
23 COM1 22 VIP1 21 VIN1 20 VCM1 19 HILO 18 ENB 17 VOH1
03199-B-081
LON1 VPS1 INH1 LMD1 LMD2 INH2 VPS2 LON2
1 2 3 4 5 6 7 8
PIN 1 INDICATOR
24 23 22 21 20 19 18 17
AD8332
TOP VIEW (Not to Scale)
COMM VOH1 VOL1 VPSV NC VOL2 VOH2 COMM
03199-C-082
9 10 11 12 13 14 15 16
RCLMP 11 VOH2 12 VOL2 13 COMM 14
16 VOL1 15 VPSV
Figure 81. 32-Lead LFCSP
Table 7. 32-Lead LFCSP (AC PACKAGE)
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Name LON1 VPS1 INH1 LMD1 LMD2 INH2 VPS2 LON2 LOP2 COM2 VIP2 VIN2 VCM2 MODE GAIN RCLMP COMM VOH2 VOL2 NC VPSV VOL1 VOH1 COMM ENBV ENBL HILO VCM1 VIN1 VIP1 COM1 LOP1 Description CH1 LNA Inverting Output CH1 LNA Supply 5 V CH1 LNA Input CH1 LNA Signal Ground CH2 LNA Signal Ground CH2 LNA Input CH2 LNA Supply 5 V CH2 LNA Inverting Output CH2 LNA Noninverting Output CH2 LNA Ground CH2 VGA Noninverting Input CH2 VGA Inverting Input CH2 Common-Mode Voltage Gain Slope Logic Input Gain Control Voltage Output Clamping Level Input VGA Ground CH2 Noninverting VGA Output CH2 Inverting VGA Output Not Connected VGA Supply 5 V CH1 Inverting VGA Output CH1 Noninverting VGA Output VGA Ground VGA Enable LNA Enable VGA Gain Range Select (HI or LO) CH1 Common-Mode Voltage CH1 VGA Inverting Input CH1 VGA Noninverting Input CH1 LNA Ground CH1 LNA Noninverting Output
Figure 80. 28-Lead TSSOP
Table 6. 28-Lead TSSOP (AR PACKAGE)
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Name LMD2 INH2 VPS2 LON2 LOP2 COM2 VIP2 VIN2 VCM2 GAIN RCLMP VOH2 VOL2 COMM VPSV VOL1 VOH1 ENB HILO VCM1 VIN1 VIP1 COM1 LOP1 LON1 VPS1 INH1 LMD1 Description CH2 LNA Signal Ground CH2 LNA Input CH2 Supply LNA 5 V CH2 LNA Inverting Output CH2 LNA Noninverting Output CH2 LNA Ground CH2 VGA Noninverting Input CH2 VGA Inverting Input CH2 Common-Mode Voltage Gain Control Voltage Output Clamping Resistor CH2 Noninverting VGA Output CH2 Inverting VGA Output VGA Ground (Both Channels) VGA Supply 5 V (Both Channels) CH1 Inverting VGA Output CH1 Noninverting VGA Output Enable--VGA/LNA VGA Gain Range Select (HI or LO) CH1 Common-Mode Voltage CH1 VGA Inverting Input CH1 VGA Noninverting Input CH1 LNA Ground CH1 LNA Noninverting Output CH1 LNA Inverting Output CH1 LNA Supply 5 V CH1 LNA Input CH1 LNA Signal Ground
Rev. C | Page 31 of 32
LOP2 COM2 VIP2 VIN2 VCM2 MODE GAIN RCLMP
AD8331/AD8332 OUTLINE DIMENSIONS
9.80 9.70 9.60
20
0.341 BSC
11
28
15
0.154 BSC
4.50 4.40 4.30 6.40 BSC
1 14
1
10
0.236 BSC
PIN 1
PIN 1 0.65 BSC 0.15 0.05 COPLANARITY 0.10 0.30 0.19 1.20 MAX 8 0 0.75 0.60 0.45
0.010 0.004 COPLANARITY 0.004
0.065 0.049
0.069 0.053
0.025 BSC
0.012 0.008
SEATING PLANE
0.20 0.09
SEATING PLANE
0.010 0.006
8 0
0.050 0.016
COMPLIANT TO JEDEC STANDARDS MO-137AD
COMPLIANT TO JEDEC STANDARDS MO-153AE
Figure 82. 28-Lead Thin Shrink Small Outline Package [TSSOP] (RU-28) Dimensions shown in millimeters
5.00 BSC SQ 0.60 MAX 0.60 MAX
25 24 32 1
Figure 84. 20 Lead Shrink Outline [QSOP] (RQ-20) Dimensions shown in millimeters
PIN 1 INDICATOR
PIN 1 INDICATOR TOP VIEW 4.75 BSC SQ
0.50 BSC
BOTTOM VIEW
3.25 3.10 SQ 2.95
8
0.50 0.40 0.30 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.30 0.23 0.18 0.20 REF
17 16
9
0.25 MIN 3.50 REF
12 MAX
1.00 0.85 0.80 SEATING PLANE
COPLANARITY 0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 83. 32-Lead Frame Chip Scale Package [LFCSP] (CP-32) Dimensions shown in millimeters
ORDERING GUIDE
AD8331/AD8332 Models AD8331ARQ AD8331ARQ-REEL AD8331ARQ-REEL7 AD8331-EVAL AD8332ARU AD8332ARU-REEL AD8332ARU-REEL7 AD8332ACP-REEL AD8332ACP-REEL7 AD8332-EVAL Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C Package Description Shrink Small Outline Package 150 mil Body, 25 mil pitch Shrink Small Outline Package 150 mil Body, 25 mil pitch Shrink Small Outline Package 150 mil Body, 25 mil pitch Evaluation Board with AD8331ARQ Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Lead Frame Chip Scale Package (LFCSP) Lead Frame Chip Scale Package (LFCSP) Evaluation Board with AD8332ARU Package Outline RQ-20 RQ-20 RQ-20 RU-28 RU-28 RU-28 CP-32 CP-32
(c) 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03199-0-11/03(C)
Rev. C | Page 32 of 32

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